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A Verilog Introduction for Hackers

By the in Technology
Sun Feb 29, 2004 at 09:23:14 AM EST
Tags: Hardware (all tags)
Hardware

Designing your own chips, the silicon variety. That's something you do with millions, if not billions of dollars of equipment and large fabrication plants under ultraclean conditions. Well, isn't it? Actually, no. You can design your own chips at home with a PC using no more than about $50 of equipment and I'm going to tell you how with the absolute minimum of effort.


I'm going to make some basic assumptions: that you vaguely know a language with C like syntax and have a vague idea that digital electronics is about manipulating binary data represented in wires by a voltage level using logic gates.

You can't design your own components completely from the ground up at home, for that you do need a lot of expensive equipment. But what you can do is program what are known as Field Programmable Gate Arrays (FPGAs) or Complex Programmable Logic Devices (CPLDs). These are large arrays of logic gates connected by a complex network that allows you to connect any gate to any other pretty much however you want. In effect you design a logic circuit on a PC that is downloaded to a chip. You can use all the usual digital components that you expect to see as discrete components: adders, flip-flops, shifters and so on. Even better, you don't even have to get your hands dirty designing circuits with these things because you can implicitly design your circuit with a high level language and have it automatically turned into a downloadable circuit.

Now here's a caveat: I'm not in any way an expert at this subject. I have no electronics background and my knowledge comes from a few hours of tinkering here and there in the evening. But I'm hoping that even though this means I'll make lots of mistakes I'll at least be able to demonstrate that this stuff really isn't that esoteric and that anyone who has basic programming knowledge can turn their hands to it.

There are a number of FPGA and CPLD development boards available but the one I'm going to talk about in this example is the Digilent XCR.

These boards use components from the company Xilinx and they provide a free development system known as Webpack. You simply plug the board in into a PC, fire up the development system, and go.

Now comes the design bit. There are two popular high level languages used for digital design: VHDL and Verilog. To my inexpert eye there is no difference betwen them except for the parser at the front end. Verilog looks like C and VHDL looks like Ada and requires developers to write a morass of syntactic glue that apparently serves no purpose. So I'll talk about Verilog. In fact, here's some sample code for you to look at. This code can be synthesized (that's like compilation but it's not called that) and downloaded directly to the XCR board with the free Webpack software.

So cast your eyes over some sample Verilog code:

module xcrdemo(mclk,ld9,btn,swt,led,an,ssg);
input mclk;
output ld9;
input [3:0] btn;
input [7:0] swt;
output [7:0] led;
output [1:0] an;
output [6:0] ssg;

reg [2:0] clkdiv;
reg [3:0] cntr;
wire cclk;
wire [6:0] dig;

assign led = swt;
assign ld9 = btn[2] | btn[3];

assign an = btn[1:0];
assign ssg = dig;

assign dig = cntr=='b0000 ? 'b0111111 :
cntr=='b0001 ? 'b0000110 :
cntr=='b0010 ? 'b1011011 :
cntr=='b0011 ? 'b1001111 :
cntr=='b0100 ? 'b1100110 :
cntr=='b0101 ? 'b1101101 :
cntr=='b0110 ? 'b1111101 :
cntr=='b0111 ? 'b0000111 :
cntr=='b1000 ? 'b1111111 :
cntr=='b1001 ? 'b1101111 :
0;

always @(posedge mclk)
begin
clkdiv<= clkdiv+1;
end

assign cclk = clkdiv[2];

always @(posedge cclk)
begin
cntr<= cntr+1;
end

endmodule

Chances are you can already guess what most of this does. I have defined a module (in this case representing the CPLD chip on the board) and I've defined a bunch of inputs and outputs. You can probably guess which is which. The brackets are used to declare arrays. For example out [7:0] led; line tells you that led in fact represents 8 output wires coming out of the CPLD. Unlike software engineers hardware engineers like to think of arrays backwards, hence the decreasing range from 7 to 0. The wire lines define internal wires within the CPLD. They are used, as you might expect, to connect things to each other.

On the XCR the 8 swt inputs are connected to switches and the 8 led outputs connect to LEDs. So assign led = swt simply says that the state of the LEDs is equal to the state of the switches. In other words, each switch turns an LED on or off.

The assign dig line is more interesting. If you can read C you'll guess immediately that it maps 4 bit numbers to 7 bit numbers. ('b means that a binary number follows) In fact the 7 bit ssg output is connected to the 7 segments of an LED display and this line performs binary to seven-segment conversion.

An important thing to note about the assign lines is that they are continuous assignments. In C if you say a=b; it means "copy the contents of b into a". In Verilog it's more like a functional language and assign a=b; means "forever more the value of a is the same as the value of b". Every one of these assign statements is running simultaneously in parallel. That might give you a clue why you might want to use these devices rather than microcontrollers for certain situations - you can have all those adders, shifters and flip flops working in parallel unlike the traditional von Neumann type machines we normally use that only perform one or two instructions at a time. Imagine how fast you can run the game of life with a bunch of logic gates dedicated to every cell.

And that now brings us to sequential logic. What happens if you want your custom designed chip to perform things sequentially? That's where the always line comes in. always @(posedge mclk) means "whenever the value of mclk goes from 0 to 1 do the following". On the XCR board the mclk input is connected to a clock with a period adjustable from a few Hz to a few KHz.

Note how clkdiv was defined to be a reg instead of a wire. This means that it is a register that has a persistent state. This means that when clkdiv <= clkdiv+1 is executed (once per clock pulse) this 3 bit register is incremented - it's more like a C assignment. Similarly the register cntr is incremented every time bit 2 of clkdiv goes from 0 to 1.

There are some other lines in the code and you can try to guess what they do.

So among other things this board displays a 4 bit count incrementing over time, though it remains blank for 0xA to 0xF. The CPLD device on the XCR board is non-volatile. This means you can simply pop it out of its socket and add it to your own circuits. Just connect up power and ground and it'll do just what your Verilog code says.

With my XCR board I have implemented a complete an entire CPU with memory in about 50 lines of code and on their DXL board I have made my own Pong game that plugs straight into a monitor with the FPGA directly controlling the voltage levels of the VGA in. This stuff is surprisingly straightforward and you get to learn a lot about how electronic devices really work at a low level.

So there you have it in a nutshell - digital design through Verilog. I'll just add one more thing about the code: to completely define how this code maps to the hardware there is another file that simply lists which pins on the chip correspond to which of the named input and output ports. The syntax is usually easy to decode once you've seen the example that comes with whichever board you decide to purchase. So go and get designing already! Even if you don't make a career of it or make a useful device for the home you'll have a deeper appreciation of just what exactly is happening inside your PC at any moment.

Further Information
There is a wealth of low cost development boards out there. Besides the Digilent boards you might like to try:

  1. The FPGAProto which comes with the verilog source to turn it into a complee 16 bit CPU. You can then hack the verilog to add your own instructions or custom I/O circuitry.
  2. The Pluto board.
  3. The BurchED.
  4. And a variety of boards are always available on Ebay.
There are many digital designs out there on the web. Example projects out there (some downloadable to synthesize on your own hardware) include:
  1. Atari 2600 on a chip.
  2. Various arcade games.
  3. Chess!
  4. Cracking DES
  5. A wealth of CPUs and computer hardware at at opencores.
  6. And the ubiquitous Pong game.
PS You don't have to use real hardware. Simulators for Verilog and VHDL exist. I've played a little with Icarus Verilog. The free commercial packages such as Webpack also come with (crippled) simulators. Watch out with simulators though - they allow you to write code at an abstract level that can be simulated but not immediately implemented in hardware. In effect Verilog doesn't just give a way to describe circuits but it also allows you to write code to simulate a circuit whose actual implementation you haven't figured out yet.

PPS One last thing: whenever I edit this story scoop incorrectly converts < in the source back to <. Sorry if it's messed up.

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A Verilog Introduction for Hackers | 80 comments (65 topical, 15 editorial, 2 hidden)
What's going on? (none / 2) (#1)
by the on Fri Feb 27, 2004 at 09:35:31 PM EST

I previewed that and all the code came out nicely. But when I submitted it looked quite different with some of the HTML being garbled. Is scoop's formatting buggy?

--
The Definite Article
Cute (none / 0) (#12)
by Psychopath on Sat Feb 28, 2004 at 05:07:43 PM EST

I really like the article and it whets the appetite to try it out! This story will go into my personal text archive :)

Are this PIC chips also FPGAs or CPLDs? Or are they something different?

Regards
--
The only antidote to mental suffering is physical pain. -- Karl Marx
Gotchas. (3.00 / 12) (#27)
by crankie on Sat Feb 28, 2004 at 08:56:01 PM EST

Nice introductory article. I used to write FPGAs (in VHDL) for a living. Given the fact that this is dubbed "an introduction for hackers", I'd like to add a few points of my own that refer specifically to things that can catch you off-guard if you come from a software background.

First, and probably most importantly, is the reset signal. On power-up, the FPGA will assert a reset line. It is vitally important that this be used to place every item in a known state. Uninitialised flip-flops can wreak havoc in what might seem like an otherwise straight-forward design.

Next is the matter of glitches. Take the following example in pseudocode:

A = X;
B = Y;
X = NOT Y;
C = A XOR B;


Now, from this, C is a tautology. Any sensible person would assume the C will be a constant, never changing value of 1. And they would be wrong. If Y changes, value, then as a result, X will change value. But this is hardware and non-sequential, but parallel evaluation occurs. Each time a signal changes, there is a propagation delay before the signals that depend on this signal are updated. This delay is not something that can be easily quantified. Indeed, the same code section will synthesise differently if the compilation is given different initial conditions. If we assume initially that it takes 1ns for every transition, then what will happen is as follows:

Y changes.
1ns later, X changes.
During that 1ns when X and Y are out of sync, the inputs to the circuit which drive signal C are the same.
C will glitch low for 1ns.

So it's quite important that you ensure that unexpected glitches don't screw you up. This is particularly important for code such as

always @(posedge C)

As this glitch will be caught by this statemeent and will have unwanted knock on effects. There are several ways to avoid such nasties. If there is sufficient interest, I may do a separate write up on such techniques. They're a bit beyond the scope of a comment though.

Other topics of interest include building effective state machines, maximising the possible operating frequency of the circuit, understanding how your code maps to the underlying hardware, functional simulation versus timing based simulation etc. Like I said, if people are interested in this, I'll do a more complete separate write-up.

~~~
"The great thing about hardcore socialists is the silence they emit once they start earning a decent wage." - tombuck
Simulation (none / 1) (#32)
by Wouter Coene on Sun Feb 29, 2004 at 11:21:23 AM EST

For people more into VHDL (mainly used in Europe, and IMO a bit more readable than Verilog), SymphonyEDA has an excellent VHDL simulator of which a free edition exists.

For more in-depth simulation, there's an addon to Xilinx' WebPACK called ModelSim, which can simulate a synthesized component. The main disadvantage of this is that your model and your testbench have to be synthesizable.

Usefulness? (none / 2) (#33)
by treat on Sun Feb 29, 2004 at 11:51:37 AM EST

Can I do something useful with an FPGA? Will certain algorithms run (much) faster than on a general purpose CPU?

I've only heard of people using FPGAs to prototype designs that will be put to silicon. This is for cost savings with high volume.

Nothing I'm doing will be built with high volume. Even if an FPGA is cheaper than a general purpose CPU, it won't be by much. To be useful for me, I would need a project that is intractable on a general purpose CPU, due to performance or other considerations.

I'm all for doing things for learning and fun. But the choice of design has to make good engineering sense.

Plug for Altera (none / 1) (#38)
by philwise on Sun Feb 29, 2004 at 12:58:22 PM EST

Altera have a freely downloadable version of their very nice IDE, Quartus II. It is limited to the cheaper end of the product line, but includes all the chips most people are likely to want to use. It only works under Windows but the full version work under Linux too.
--
(presenter) "So, altogether now, what are we?"
(audience) "We are all Free Thinkers."
VHDL (none / 1) (#40)
by crazycanuck on Sun Feb 29, 2004 at 01:04:36 PM EST

I know VHDL and not Verilog.
What is this "useless glue logic" of which you speak?

(BTW: a VHDL model is required for any chip/system submitted to the US military. that's how VHDL started, in the DOD)

OpenSores (1.00 / 6) (#53)
by dimaq on Mon Mar 01, 2004 at 09:14:55 AM EST

the author is welcome to mention that nearly all the software one might use to make the cycle of design, verification and synthesis is proprietary and runs on propriatary operating systems. and that *all* of usable software is/does.

VHDL and programming mindset (none / 1) (#63)
by Paul Hodson on Tue Mar 02, 2004 at 03:37:14 PM EST

Interesting article. For quite a while I've been interested in learning Verilog (I do all my FPGA development in VHDL), and a little kick in the right direction is always welcome.

One thing I very much like about VHDL is how it is different from most programming languages (Ada aside). It forces that the programmer adopt a different mindset when writing logic, which to me is a great thing since "hardware programming" is very different from software programming.

When you're "writing" hardware (as is the case for FPGAs and other reconfigurable devices), you have to design your code such that it operates in parallel, or you have to at the very least be aware of what will operate in parallel or in sequence. VHDL, being a structurally and syntactically different language from C and others, already starts the process of converting the mindset. I find its differences very refreshing.



VHDL for synthesizeable code (none / 1) (#67)
by khayman on Wed Mar 03, 2004 at 01:43:40 PM EST

I find the syntax imposed by VHDL help people coming from a sw background making synthesizeable code.

FPGA versus CPLD... (none / 0) (#72)
by Cryptnotic on Fri Mar 05, 2004 at 10:40:55 PM EST

One problem with FPGA's is that when you power them up, they're blank. When you're developing, this is fine since you'll be downloading a configuration from your PC onto the FPGA for testing. When you're making a product, it's a bit of a problem and increases the cost of your design. Some FPGA's will automatically configure themselves via something like a serial EEPROM, so you put an EEPROM onto the board and the FPGA configures off of that. PLD's (Programmable Logic Devices) or CPLD's (In-system Configurable PLD's) are another option, but they are nowhere near the density of FPGA's. On the other hand, they are cheaper. If all you need is a couple of logic gates or flip-flops, then that's what you'd use. No one uses discrete logic anymore. Well, that's not entirely true. Discrete logic chips are dirt cheap (3 cents for a NAND gate maybe?). But if you need more than a few of them or you need some configurability, then you'll use a PLD variant.

A Verilog Introduction for Hackers | 80 comments (65 topical, 15 editorial, 2 hidden)
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